The present invention generally relates to semiconductor processing, and in particular to a system and method for facilitating wafer alignment by mitigating effects of reticle rotation on overlay.
The tendency of semiconductor devices such as integrated circuits (IC) and large scale integrated circuits (LSIC) toward minuteness has rapidly progressed, and higher accuracy has been required of apparatuses for manufacturing such semiconductor devices. In particular, such requirements are demanded from exposure devices in which a circuit pattern of a mask or a reticle is superposedly transferred onto a circuit pattern formed on a semiconductor wafer. It is desired that the circuit pattern of the mask and the circuit pattern of the wafer be superposed one upon the other with accuracies of, for example, less than 0.1 xcexcm.
Semiconductor integrated circuits undergo a variety of processing steps during manufacture, such as masking, resist coating, etching, and deposition. In many of these steps, material is overlayed or removed from the existing layer at specific locations in order to form desired elements of the integrated circuit. Proper alignment of the various process layers is important. The shrinking dimensions of modern integrated circuits require increasingly stringent overlay alignment accuracy. If proper alignment tolerances are not achieved, device defects can result.
More particularly, during fabrication of an IC, a wafer lithography system projects a pattern of light onto a photoresist layer of a wafer. The projected light changes properties of exposed portions of the photoresist layer such that a subsequent development process forms a mask from the photoresist layer which exposes or protects different portions of the wafer. The masked wafer is then removed to a reaction chamber where a process such as etching changes the exposed portions of the wafer. Typically, a wafer lithography system forms several masks on a wafer during an IC fabrication process, and the masks must be aligned with each other to form a working IC.
A wafer stepper typically is used to align the wafer during the various process steps. The wafer stepper uses one of a number of commercially available techniques to generate alignment signals which indicate position relative to the wafer. The alignment signals typically are produced by optical measurement of alignment marks placed at specified locations on the wafer. A reticle is used to place the appropriate marks on a particular wafer process layer such that the marks can be readily identified by the wafer stepper in subsequent processing steps. The reticle includes a pattern which can be etched into the wafer using optical photolithography. Commonly used alignment mark techniques include Laser Step Alignment (LSA), Field Image Alignment (FIA), Laser Interferometric Alignment (LIA), Global Alignment Mark (GAM), and Global Alignment Mark Laser Step Alignment (GAMLSA). In a step-and-repeat type apparatus, the wafer is moved in steps by predetermined distances. For example, the wafer typically is placed on a two-dimensionally moveable stage and positioned relative to a projected image of a reduction projection type exposure apparatus.
Some types of alignment systems and/or methods employ large global alignment marks to align the wafer. For such systems and/or methods, a reticle includes a design pattern and an alignment mark. The alignment mark is typically located outside of the design pattern, although the alignment mark could be located within the design region but at the expense of sacrificing design area real estate. The design pattern and alignment mark are printed at several predetermined fields of a wafer. These printed alignment marks are found by a stepper system and are employed in wafer alignment, for example, for subsequent processing.
Another type of alignment system utilizes a reticle having scribe lines located along a perimeter portion of the design area. Usually, two sets of scribe lines are printed respectively along two adjacent sides of the design area, with each set of scribe lines having a standard pitch. The scribe lines and design pattern are printed at several predetermined fields of the wafer during a step-and-repeat process. The printed scribe lines extend between each adjacent field. A stepper system locates, for example, a centroid for a selected set of scribe lines to facilitate alignment between the reticle and the wafer in subsequent processing.
However, the reticle may have been positioned in the projection system with a slight rotation and/or the reticle may include rotation errors due to the scribe lines and associated design pattern being slightly rotated or shifted (for example, as a result of error in the process of manufacturing the reticle). The errors due to rotation or shifting of the scribe lines and design pattern become greatly exaggerated as one moves away from the center of the reticle. Another type of error is lens magnification error wherein the image (scribe lines and/or design pattern) is slightly over-magnified or under-magnified with respect to an intended magnification level. The reticle rotation error and/or lens magnification error result in the scribe lines being printed at locations different from intended. Consequently, the centroid position which is used for alignment purposes also includes position errors proportional to the reticle rotation error.
The present invention relates to a system and method for facilitating wafer alignment by mitigating overlay error in the production of semiconductor devices.
One aspect of the present invention relates to a method for determining a reference point on a wafer. A composite set of scribe marks is formed from a first and second set of scribe marks. The composite set of scribe marks has a geometric characteristic which substantially negates rotational error associated with a reticle employed in a lithographic printing process.
Another aspect of the present invention relates to a method for facilitating wafer alignment using a reticle. The reticle includes a design area, a first set of scribe marks, and a second set of scribe marks symmetric to the first set of scribe marks relative to the design area. The first and second sets of scribe marks are printed on a surface layer of the wafer associated with a first field location. The first and second sets of scribe marks are printed on the surface layer of the wafer associated with a second field location adjacent to the first field location, such that the first set of printed scribe marks of the first field location and the second set of printed scribe marks of the second field location form a composite set of printed scribe marks, which substantially negates rotational error associated with the reticle employed in a lithographic printing process.
Still another aspect of the present invention relates to a reticle for use in a lithographic process. The reticle includes a design area, a first set of scribe marks located along a first side of the design area, and a second set of scribe marks located along a second side of the design area opposite the first side. The first and second sets of scribe marks have an associated symmetry relative to the design area such that, upon being printed onto adjacent fields of a wafer, the first set of printed scribe marks of one of the adjacent fields and the second set of printed scribe marks of another of the adjacent fields reticulate to form a composite set of printed scribe marks, which substantially negates rotational error associated with the reticle employed in a lithographic printing process.
Yet another aspect of the present invention relates to a system for facilitating wafer alignment. The system includes a reticle including a design area, a first set of scribe marks located along a first side of the design area, and a second set of scribe marks located along a second side of the design area symmetric to the first set of scribe marks relative to the design area. The system includes at least one system for locating a composite set of scribe marks as printed on a surface layer of the wafer, the composite set of scribe marks being formed by aggregating the first set of scribe marks as printed on the surface layer associated with a first field location and the second set of second marks as printed on the surface layer associated with a second field location adjacent to the first field location. A processor controls general operations of the at least one system and determines a geometric characteristic of the composite set of printed scribe marks. The processor employs the geometric characteristic to facilitate alignment of the wafer.
Another aspect of the present invention relates to a system for aligning a wafer. The system includes means for locating a composite set of scribe marks on a surface layer of the wafer, the composite set of scribe marks being formed from a first and second set of scribe marks printed on the surface layer of the wafer respectively associated with first and second adjacent fields, the first and second sets of printed scribe marks having an associated symmetry such that the composite set of scribe marks substantially negates reticle rotation error. The system also includes means for determining a geometric characteristic of the composite set of scribe marks, the geometric characteristic being a virtual alignment mark, and means for aligning the wafer using the virtual alignment mark as a reference.
To the accomplishment of the foregoing and related ends, the invention, then, comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.